The present invention relates to an SOI semiconductor device employing an SOI substrate and a method for producing the same.
In production of semiconductor devices, high purity semiconductor substrates are used, but heavy metals slightly contained in a semiconductor substrate cause junction leakage in a semiconductor element, or a reduction in the withstand voltage of a gate oxide film. Therefore, the presence of heavy metals is not preferable.
With respect to such heavy metal contamination, in general, an approach called xe2x80x9cgetteringxe2x80x9d is used to capture heavy metals to keep the heavy metals away from a semiconductor device, and thus the heavy metals are prevented from affecting the characteristics of a semiconductor device to be produced. A specific example of this approach is a brush damage method. In this method, a brush damage is caused on the back face of a semiconductor substrate to let this damaged layer capture heavy metals, so that the heavy metals are prevented from affecting the characteristics of a semiconductor element.
However, when producing an SOI semiconductor device employing an SOI substrate, this method cannot be used, because in SOI semiconductor devices, a semiconductor element is formed in an SOI active layer separated from a semiconductor substrate by a buried oxide film. That is to say, some heavy metals cannot pass through the buried oxide film, so that the damaged layer formed on the back face of the semiconductor substrate cannot prevent heavy metal contamination. Therefore, there is a demand for development of a gettering method for heavy metals suitable for SOI semiconductor devices.
A gettering method for an SOI semiconductor device that can solve this problem is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2000-315736. A conventional SOI semiconductor device will be described with reference to FIG. 18.
FIG. 18A shows the planar structure of a CMOS transistor of a conventional SOI semiconductor device, and FIG. 18B shows the cross-sectional structure taken along line Y-Yxe2x80x2 in FIG. 18A.
In the structures shown in FIGS. 18A and 18B, an n-type semiconductor layer 103 that will serve as an active layer of an SOI substrate is formed on a semiconductor substrate 101 that is a supporting substrate in an SOI substrate via a silicon oxide film 102 that is a first insulating film. The nxe2x88x92-type semiconductor layer 103 is isolated in the form of an island by dielectrics, using the silicon oxide films 102 and 105. More specifically, an isolating groove 104 that reaches up to the buried silicon oxide film 102 is formed by etching, and then the silicon oxide film 105 serving as an insulating film is formed on the side wall portion of the isolating groove 104. Then, a polysilicon layer 106 is buried and thus the nxe2x88x92-type semiconductor layer 103 is isolated in the form of an island by the silicon oxide film 102 and the silicon oxide film 105.
In the thus formed island-shaped nxe2x88x92-type semiconductor layer 103, an n-type semiconductor layer 122 serving as an N well of a P channel MOS transistor, a p-type semiconductor layer 123 serving as a P well of an N channel MOS transistor, and a highly doped impurity diffusion region (p+ layer) 110 for the gettering of heavy metals are formed. In other words, the highly doped impurity diffusion region (p+layer) 110 is formed in each of a plurality of nxe2x88x92-type semiconductor layers 103 isolated in the form of an island. Furthermore, gate oxide films 125a and 125b, gate electrodes 124a and 124b, p+-type semiconductor layers 126a and 126b for forming a drain region and a source region of a P channel MOS transistor, and n+-type semiconductor layers 127a and 127b that will serve as a drain region and a source region of an N channel MOS transistor are formed. Further, wires are formed in this structure and thus a CMOS transistor is produced.
In this CMOS transistor, when the highly doped impurity diffusion region 110 is formed of boron, which is a p type impurity, and the concentration on the surface thereof is 1xc3x971018 atoms/cm3 or more and 5xc3x971020 atoms/cm3 or less, then the gettering of heavy metals is achieved by the highly doped impurity diffusion region 110, and thus junction leakage and reduction of the withstand voltage of gate oxide films can be prevented.
However, the inventors of the present invention found the following problem. In the above-described conventional SOI semiconductor device, crystal defects occur in the periphery of the captured heavy metals, so that it is necessary to space the highly doped impurity diffusion region 110 apart from the PN junction by a sufficient distance, which increases the size of a single semiconductor element, and consequently the size of a semiconductor chip is increased. That is to say, in the above-described SOI semiconductor device, the highly doped impurity diffusion region 110 is formed in the same island isolated by insulating films in which a semiconductor element is formed (or the highly doped impurity diffusion region 110 is formed very near an active region). Therefore, the size of the semiconductor element is increased. In the above publication, a method for forming the highly doped impurity diffusion region 110 straddling the isolating groove 104 that forms an isolated region is also proposed. However, in this case, since the highly doped impurity diffusion region 110 is spread in the horizontal direction at the time of diffusion, the gettering layer (the impurity diffusion region 110) is spread up to the inside of the semiconductor element. Therefore, as a result of ensuring the distance from the impurity diffusion region to the PN junction, a single semiconductor element becomes large, so that the entire semiconductor chip becomes large.
Therefore, with the foregoing in mind, it is a main object of the present invention to provide a compact SOI semiconductor device and a method for producing the same.
An SOI semiconductor device of the present invention includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.
It is preferable that the surface concentration of the high concentration impurity in the gettering layer is 1xc3x971018 atoms/cm3 or more.
It is preferable that a plurality of active semiconductor elements are formed in the semiconductor layer, and all the active semiconductor elements are positioned within a distance of 1.5 mm from the gettering layer.
In one preferable embodiment, at least one of an N type well and a P type well is formed in the element formation region, and a depth of the gettering layer is substantially the same as or deeper than that of the well.
In one preferable embodiment, a plurality of active semiconductor elements are formed in one of the element formation regions, and the gettering layer is formed outside the isolating region surrounding the element formation region.
In one preferable embodiment, the gettering layer is provided apart from the isolating region.
In one preferable embodiment, the SOI substrate includes a silicon substrate, the insulating film formed on the silicon substrate, and an SOI active layer formed on the insulating film. The semiconductor layer is an SOI active layer made of silicon. The SOI active layer includes at least a transistor as the active semiconductor element. The gettering layer is not formed within a region in which the active semiconductor element is formed.
In one preferable embodiment, the SOI semiconductor device is a semiconductor chip. At least one power wire of a power wire on a low potential side and a power wire on a high potential side is provided in a peripheral region of the semiconductor chip. The gettering layer is formed in a semiconductor layer positioned directly below the power wire.
The gettering layer may be electrically connected to the power wire.
In one preferable embodiment, the SOI semiconductor device has a wafer structure including a plurality of semiconductor chip regions, each of which becomes a semiconductor chip when the plurality of semiconductor chip regions are cut. The SOI semiconductor device having the wafer structure includes a scribe lane that is a boundary portion of adjacent semiconductor chip regions and has the gettering layer in at least a portion of the semiconductor layer within the scribe lane.
In one preferable embodiment, the SOI semiconductor device is a semiconductor chip, a plurality of bonding pads are provided along a periphery of the semiconductor chip, and the gettering layer is provided directly below or a peripheral portion of at least one of the plurality of bonding pads.
The gettering layer can be provided directly below a region within 30 xcexcm from an outer edge of the at least one bonding pad, the region including a region within said bonding pad.
In one preferable embodiment, the SOI semiconductor device has at least one of a bus wire, a power wire and a ground wire, and the gettering layer is provided below at least one of the bus wire, the power wire and the ground wire.
In one preferable embodiment, a passive semiconductor element is formed on the semiconductor layer via an insulating film. The gettering layer is formed in the semiconductor layer positioned below the passive semiconductor element. The passive semiconductor element is at least one of a capacitor and a polycrystalline silicon resistor.
In one preferable embodiment, the SOI semiconductor device includes a plurality of circuit blocks. Each of the plurality of circuit blocks has a length of one side of 3 mm or less. The gettering layer is provided in a periphery of each of the plurality of circuit blocks.
In one preferable embodiment, the SOI semiconductor device includes an output transistor. The output transistor is separated into a plurality of blocks such that the length of one side thereof is 3 mm or less. The gettering layer is provided in a periphery of each of the plurality of blocks.
In one preferable embodiment, the SOI semiconductor device includes a large-scale logic circuit. The large-scale logic circuit is divided into a plurality of blocks such that the length of one side thereof is 3 mm or less. The gettering layer is provided in a periphery of each of the plurality of blocks.
A first method for producing an SOI semiconductor device of the present invention includes the steps of preparing an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; forming a gettering layer containing a high concentration impurity selectively in a portion on a surface of the semiconductor layer excluding an element formation intended region in which an active semiconductor element is to be formed; performing a heat treatment for facilitating gettering of heavy metals contained in the semiconductor layer after the step of forming the gettering layer or in the same step; forming an isolating region in the semiconductor layer such that the element formation intended region is isolated in a form of an island after the heat treatment; and forming an active semiconductor element in the element formation intended region surrounded by the isolating region.
A second method for producing an SOI semiconductor device of the present invention includes the steps of preparing an SOI substrate including an SOI active layer made of a semiconductor; forming a gettering layer containing a high concentration impurity selectively in a portion on a surface of the SOI active layer excluding an element formation intended region in which an active semiconductor element is to be formed; introducing an impurity for forming a well in the element formation intended region on the surface of the SOI active layer after the gettering layer is formed; performing a heat treatment so as to drive the impurity in to form a well in the element formation intended region after the gettering layer is formed; and forming an isolating region in the semiconductor layer such that the element formation intended region is isolated in a form of an island after the heat treatment.
A third method for producing an SOI semiconductor device of the present invention includes the steps of preparing an SOI substrate including an SOI active layer made of a semiconductor; introducing a high concentration impurity so as to form a gettering layer selectively in a portion on a surface of the SOI active layer excluding an element formation intended region in which an active semiconductor element is to be formed; introducing an impurity for forming a well in the element formation intended region on the surface of the SOI active layer; performing a heat treatment so as to drive the impurity in to form a well in the element formation intended region and to facilitate gettering; and forming an isolating region in the semiconductor layer such that the element formation intended region is isolated in a form of an island after the heat treatment.
A fourth method for producing an SOI semiconductor device of the present invention includes the steps of preparing an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; forming a gettering layer containing a high concentration impurity in a portion on a surface of the semiconductor layer excluding an element formation intended region in which an active semiconductor element is to be formed; selectively introducing an impurity for forming a well in the element formation intended region and then performing a heat treatment so as to form a well; forming an isolating region surrounding the element formation intended region of the semiconductor layer such that the gettering layer is not included in the element formation intended region; and forming an active semiconductor element in the element formation intended region.
In one preferable embodiment, the step of forming the gettering layer includes the steps of forming an oxide film mask having an opening in a predetermined area on the semiconductor layer; introducing a high concentration impurity in the semiconductor layer through the opening of the oxide film mask; and etching the oxide film mask after the high concentration impurity is introduced. In the step of forming the gettering layer, a difference in level that is formed in the predetermined area of the semiconductor layer is used as a reference for aligning masks to be subsequently used.
In one preferable embodiment, the surface concentration of the high concentration impurity in the gettering layer is 1xc3x971018 atoms/cm3 or more.
In one preferable embodiment, the prepared SOI semiconductor device is a wafer including a plurality of semiconductor chip regions, each of which becomes a semiconductor chip when the plurality of semiconductor chip regions are cut. Each of the semiconductor ship regions includes at least one region selected from the group consisting of a region in which a ground wire is provided, a region in which a bus wire is provided, a region in which a power wire is provided, a region in which a bonding pad is provided and a region in which a passive semiconductor element is provided, and a plurality of element formation intended regions. The gettering layer is formed in the semiconductor layer in the at least one region.
In one preferable embodiment, the prepared SOI semiconductor device is a wafer including a plurality of semiconductor chip regions, each of which becomes a semiconductor chip when the plurality of semiconductor chip regions are cut. A boundary portion of adjacent semiconductor chip regions is used as a scribe lane, and the gettering layer is formed in the semiconductor layer within the scribe lane.
In one preferable embodiment, the prepared SOI semiconductor device is a wafer including a plurality of semiconductor chip regions, each of which becomes a semiconductor chip when the plurality of semiconductor chip regions are cut. Each of the semiconductor chip regions includes a plurality of regions for forming circuit blocks. Each of the plurality of regions for forming circuit blocks has a length of one side of 3 mm or less. The gettering layer is formed in the semiconductor layer positioned around each of the plurality of regions for forming circuit blocks.
Another SOI semiconductor device of the present invention includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer for capturing heavy metals in the semiconductor layer is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.
The gettering layer may be a damage layer having lattice defects that can capture the heavy metals in the semiconductor layer.
According to the present invention, the gettering layer is not formed in the element formation region in which an active semiconductor element is formed, so that a compact SOI semiconductor can be realized.
According to the present invention, the gettering layer is formed in a portion of the semiconductor layer excluding the element formation region in which an active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which an active semiconductor element is formed. Therefore, a compact SOI semiconductor can be provided.